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Munich October 18—Come See SystemC Evolution Day!
Sorry, you missed Oktoberfest (which is mostly in September anyway). But come to Munich in October for SystemC Evolution Day—a workshop on the evolution of SystemC standards held in Munich, Germany on...
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Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on...
On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic Simulation on Arm-based servers. It was demonstrated running on Cavium ThunderX2 and Qualcomm Centriq servers at the...
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Adding Annotations in Your e Code
If you have had a chance to work with languages like Java or C#, you might have come across Annotations. Since the Specman 17.10 version, annotations have become part of the e language! (See Java...
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Slaying the Gate-Level Simulation (GLS) Dragon: Your Knight Is Here!
Even today, gate-level simulation is still a major signoff step for most semiconductor projects. However, those simulations can take days or weeks to run. A bug that causes a rerun of a gate regression...
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26262 4U: Infineon and the Incisive Functional Safety Simulator
Infineon and Cadence have a bit of a history: they’ve been working together on functional safety mechanisms for around two and a half years now, and Infineon has been using the entire Cadence...
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Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With...
On November 28, 2017, Cadence announced the release of the first available PCIe® 5.0 Verification IP. This new VIP gives designers access to Cadence’s TripleCheck technology—which gives designers a...
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Register for the UVM Register Layer Webinar on January 12!
On Friday, January 12, Doulos is hosting a UVM Register Layer webinar, with the aim of helping users model UVM in certain less-intuitive ways. This webinar will cover the usage of user-defined front...
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App Note Spotlight - Introduction to Connect Modules
Welcome to the App Note Spotlight—a bi-weekly series where the XTeam highlights an app note that contains valuable information you may not be aware of. Today, we're going to look at connect...
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User Extensions to DUT Error
A question was raised to stackoverflow about how can one extend the dut_error() for printing more information. The capability to provide the test runners and debuggers more information upon an error...
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CRAFTing Your Aero/Defense UVM Testbench the Easy Way
So you want to build an automated testbench for your aero/defense project, eh? Luckily, there’s a solution for you. A project called CRAFT (which stands for Circuit Realization At...
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This Was 2017, Looking Forward 2018
With 2017 just out of the door, this is a good time to stop for a few minutes, look back at 2017, and plan ahead for 2018 and the years to come.While thinking of the projects and challenges awaiting...
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App Note Spotlight: SystemVerilog Gets a Real Number Modeling Update (SVRNM)
Thanks to Xcelium, there’s a new feature on the block in SystemVerilog. It pertains to real number modeling (SVRNM), and it both enhances and simplifies the design of mixed-signal circuits.How? Well,...
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Type MIN / MAX Values in Specman
When defining coverage bins for coverage items, the number and size of bins depend on the item type. People seek ways to define the MIN and MAX value of the type automatically, rather than typing the...
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Coming to DVCon? It's Not Too Late to Sign Up!
Are you coming to DVCon this year? It’s right around the corner, but it’s not too late to register! DVCon is the flagship conference for all things functional design and verification, showcasing the...
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Xcelium and Cavium: What’s the Deal?
So—you may have heard that Xcelium Parallel Simulator is available on Arm servers now. While that’s all well and good, why is it such a big deal? Well, Cadence gathered up Ziv Binyamini, Gopal Hegde,...
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App Note Spotlight: Choosing the Incremental Elaboration Flow That’s Right...
Welcome to another App Note Spotlight!One of the biggest issues facing verification engineers is the question of reducing elaboration time. Using incremental elaboration (MSIE) can greatly reduce that...
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Temporals, Reset, and Test Phases
One of the biggest challenges in dynamic functional verification is testing Reset – resetting the DUT during simulation and check DUT operation afterwards. The main challenges are propagating the reset...
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App Note Spotlight: Streamline Your SystemVerilog Code, Part I
Welcome to a special multi-part edition of the App Note Spotlight, where we’ll be highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for...
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List of TLM Analysis Ports: Where Is This Packet Coming From?
Let’s say that you got an invitation from the police station nearest your home to be there the next day at 14:00. Hmm…. What could it be about? You check the letter and envelope for more information,...
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Xcelium's New Save and Restart Saves You Time
You may have heard about the overhaul to the old save/restart mechanism that was in Incisive—but are you aware of what the new Xcelium Simulator version can do?While the old version is still supported,...
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