Clik here to view.
Leading the Charge: Cadence Announces New Verification IP for UFS 3.0,...
Today, Cadence announced three new VIPs, two of which are industry-firsts! Cadence revealed the first available VIP for CoaXPress for high-speed imaging and the first available VIP for HyperRAM...
View ArticleClik here to view.
Empowering Generation - Range Generated Fields (RGF)
Specman constraints solver process consists of a series of reductionsand assignments. It reducesthe range of the field value based on the constraints, and then assignsto it a random value from the...
View ArticleClik here to view.
App Note Spotlight: Streamline Your SystemVerilog Code, Part II -...
Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines...
View ArticleClik here to view.
RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs
The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to...
View ArticleClik here to view.
Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load
Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April...
View ArticleClik here to view.
DMS 2.0 - What's Cool and What's New
Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and...
View ArticleClik here to view.
Is it Time to Verify Your Chips in the Cloud? Part 1 of 3
Welcome to the first installment of a three-part blog series examining the issues and opportunities for performing verification in the cloud.For a while now, there’s been a growing interest in...
View ArticleClik here to view.
App Note Spotlight: Streamline Your SystemVerilog Code, Part III -...
Welcome back to the third installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation...
View ArticleClik here to view.
Is It Time to Verify Your Chips in the Cloud? Part 2 of 3
Welcome back to our series on cloud verification solutions. This is part two of a three-part blog—you can read part one here.The high-performance computing (HPC) market continues to grow. Analysts say...
View ArticleClik here to view.
UVM-ML- Managers’ Freedom of Choice
Freedom of choice is a term we hear a lot, especially in the last 10 years. It is defined in wikipedia as “an individual's opportunity and autonomy to perform an action selected from at least two...
View ArticleClik here to view.
Is it Time to Verify Your Chips in the Cloud? Part 3 of 3
Welcome back to our series on cloud verification solutions. This is the final part of a three-part blog—you can read part one here and part two here.Now, for the moment you’ve all been waiting for:...
View ArticleClik here to view.
Tales From DAC: How Syntiant Went From Zero to Tapeout in Six Months
Here’s something to chew on:Syntiant is an AI startup involved in deep learning technology and semiconductor design. Their goal is to create exceptionally low-power designs for always-on devices, like...
View ArticleClik here to view.
Tales from DAC: How Altia Systems Used Xcelium to Bring New Life to Virtual...
We’re going to take a wild guess and say you’ve been in a meeting before. Maybe it was a virtual meeting—but those never really feel the same in person, do they? Attending a virtual meeting can feel...
View ArticleClik here to view.
App Note Spotlight: Streamline Your SystemVerilog Code, Part II -...
Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines...
View ArticleClik here to view.
Tales From DAC: Netspeed and the Cadence Interconnect Workbench Pair Up
Services like facial detection, efficient cloud server workload management, artificial intelligence, and image enhancement are all the rage these days; but creating a design to accommodate these needs...
View ArticleClik here to view.
Adding a Patch Just in Time! — Or Can You Really Allow Yourself to Waste So...
One animation video - Patch Like The Wind - is worth a thousand words :)If you don’t use Specman or don’t use Specman correctly, you spend most of your time waiting for compilation to finish.One of...
View ArticleClik here to view.
Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos
Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling...
View ArticleClik here to view.
App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic...
Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation...
View ArticleClik here to view.
Specman 18.09: Avoiding the Small Annoying Mistakes
Specman 18.09: Avoiding the Small Annoying Mistakes In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article...
View ArticleClik here to view.
Improving Your Testbench Flexibility with Enhanced Specman Templates
Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible...
View Article