Clik here to view.
Introduction of High Bandwidth Embedded USB2v2 (eUSB2v2) Standard
Universal Serial Bus (USB) technology is the most popular connector in every computing device, but when it comes to embedded applications, where only a specific device function may be required, the...
View ArticleClik here to view.
Unraveling Orthogonal Header Content (OHC) in PCIe 6.0
Introduction With the arrival of Flit Mode, the information hold by the TLP header was reorganized. In addition to the base header, Orthogonal Header Content (OHC) may be added into the TLP. OHC works...
View ArticleClik here to view.
Various Types of Transaction-Based Interfaces (TLM) for DisplayPort VIP
IntroductionDifferent RTL designs often require different specially designed parallel interfaces. These different interface requirements serve varying needs, such as certain blocks not being ready when...
View ArticleClik here to view.
Understanding Extended Metadata in CXL 3.1: What It Means for Your Systems
As technology continues to advance, so do the ways we connect and manage memory and devices in our computing systems. The latest version of Compute Express Link (CXL) 3.1 introduces a feature known as...
View ArticleClik here to view.
AMBA LTI Verification IP for Arm System MMU
The AMBA LTI (Local Translation Interface) defines the point-to-point protocol between an I/O device and the TLBU (Translation Buffer Unit) of an Arm System Memory Management (SMMU). The LTI protocol...
View ArticleClik here to view.
Cadence Announces Industry's First Verification IP for Embedded USB2v2 (eUSB2v2)
USB Promoter Group has released the eUSB2® Version 2.0 specification (eUSB2v2) in August 2024, which is developed to deliver a scalable I/O technology, specifically designed for inside-the-box...
View ArticleClik here to view.
Cadence's 2024 Training Programs and Resources
As we welcome 2025, let’s take a moment to reflect on the most viewed blogs and videos of the past year and review the developments in education throughout 2024.During 2024, we released eight...
View ArticleClik here to view.
Time on Your Side: Launching PSS Perspec Composer
We all agree that time is precious. As PSS (Portable Stimuli Standard) models get larger, the time it takes for the whole model to be loaded in Cadence Perspec Composer might become meaningful. In this...
View ArticleClik here to view.
USB4 Port Operations
Designs are tested in the labs for various electrical compliance tests defined in the electrical compliance test specifications before getting certified. There are defined processes and steps that a...
View ArticleClik here to view.
Training Insights – Tcl Scripting Course for Beginner and Advanced Users
Tcl is a versatile scripting language used in automation, testing, networking, and more. Tcl plays a crucial role in Electronic Design Automation (EDA) tools used in the VLSI industry.Leading EDA tools...
View ArticleClik here to view.
Unlocking Efficient Debugging with the Verisium WaveMiner App
Overview of the Verisium WaveMiner AppVerisium WaveMiner is part of the Verisium suite of AI-driven verification tools that automate the root cause analysis of misbehavior introduced between two...
View ArticleClik here to view.
NOP Flit Payload: A Dedicated Debug Channel
Modern PCIe systems are complex, with high-speed data transfer and intricate protocols. Traditional debug methods often struggle to provide the necessary granularity and real-time visibility into link...
View ArticleClik here to view.
Using PSS Registers with Perspec for Portable Programming Sequences
When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus Standard (PSS) to model your system, you will likely need a way to operate on the memory-mapped registers of various...
View ArticleClik here to view.
eMMC: The Embedded Storage Powering On-Device AI
In today's world of increasingly intelligent devices, efficient and reliable storage is paramount. Embedded MultiMediaCard (eMMC) has emerged as a crucial component that acts as the internal...
View ArticleClik here to view.
UALink: Powering the Future of AI Compute
On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification, marking an important milestone with support from key hyperscalar market players. It enables a low-latency,...
View Article