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Creating Code from Tables
Some things are best described with tables—each column shows the values for one category, and each row encapsulates one given set of values for all categories.This blog describes how to use tables in...
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IEEE Std 1647™ 2016 - e Language - New Standard Publication
Congratulations to the IEEE-1647 e Functional Verification Language Working Group (eWG)In the beginning of 2017, the IEEE-1647 eWG issued for publication IEEE Std 1647™ 2016, IEEE Standard for the...
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Specman in Xcelium
Just recently Cadence announced the new superb simulator, Xcelium. Just as Specman was part of the previous simulator, IES, it is now part of Xcelium.As always, we keep enhancing and developing...
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Static Members in e
How do you define elegant or clean code? Usually, you know it when you see it; defining it is harder. It is usually a simple, clear and well-structured code. OO programming languages (like Java, C++,...
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A Brief Introduction to Xcelium
Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the newest in parallel simulation technology with the Xcelium Parallel Simulator. In this blog, we will bring you...
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X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset
All chips need to cold reset on every power-up. Warm resets, however, are a bit more complicated. Take a smartphone screen, for example. The screen may power down while the phone is idle. However, the...
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Cadence @ DAC: What to Expect and What to See
Cadence returns to DAC 2017 this year, showcasing our full verification suite. Here are some of the things you can look forward to from us in the upcoming week.Once again, Cadence has the Expert Bar on...
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Single Core vs. Multi Core: Simulation in Stereo
Latency simulations are the sworn enemy of the verification schedule. A handful of tests add days to weeks for each regression cycle; and when you add in the fact that they can’t be parallelized like...
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Save & Restore with More: Preserve Your Entire SoC
The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and...
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Enum compatibility error in Specman
One of my favorite quotes about SW programming is the following by Edsger Dijkstra: "If debugging is the process of removing software bugs, then programming must be the process of putting them in."...
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Xperiences with Xcelium: Hewett-Packard Enterprise Makes the Switch
At Hewlett-Packard Enterprise (HPE), the team working to create IP for “The Machine,” HPE’s vision for the future of computing, recently decided to make the switch to the Xcelium Simulator from their...
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ROHM CO., Ltd Adopts Our Functional Safety Verification Solution
On July 17, 2017, Cadence announced that the Cadence® Functional Safety Verification Solution had been adopted by ROHM CO., Ltd as part of its deisgn flow for ISO 26262-compliant ICs and LSIs for the...
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X-Propagation: Xcelium Simulator’s X-prop Technology Ensures Deterministic Reset
All chips need to cold reset on every power-up. Warm resets, however, are a bit more complicated. Take a smartphone screen, for example. The screen may power down while the phone is idle. However, the...
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Moving to Xcelium Simulation? I’m Glad You Asked
Ready to take the next step in simulation technology with a true third-generation engine, with multi-core technology? Cadence® Xcelium™ Simulator allows you to have unprecedented control over your...
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Infineon’s Coverage-Driven Distribution: Shortcutting the MDV Loop
There are more ways to improve productivity in the verification process than simply making the simulation run faster. One of these is to cut down on the amount of time engineers spend working hands-on...
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Put On Your Perspectacles: How Perspec Can Speed Up Your Testbench
It’s no secret that the bulk of time running simulations is spent on the testbench side. You can throw as many cores as you want at the DUT when you’re running RTL tests, but let's face it, it’s the...
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A Brief Introduction to Xcelium
Welcome to the XTeam blog! We are a team of bloggers dedicated to showcasing the newest in parallel simulation technology with the Xcelium Parallel Simulator. In this blog, we will bring you...
View ArticleClik here to view.
Single Core vs. Multi Core: Simulation in Stereo
Latency simulations are the sworn enemy of the verification schedule. A handful of tests add days to weeks for each regression cycle; and when you add in the fact that they can’t be parallelized like...
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Teradyne "Formally" Adopts JasperGold FPV
CDNLive Boston 2017: Teradyne reveals their success with JasperGold in their presentation, Success using Formal Verification--and now they join the ever-growing fold of JasperGold FPV (Formal Property...
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Teradyne Standardizes on Xcelium Simulator
Today, Cadence announced that Teradyne has adopted the Xcelium™ Parallel Simulator for use in ASIC development. They’ve reached a 2x speedup with Xcelium when compared to their old simulation...
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