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Multi-Language Verification Environment—Getting First Run in Few Minutes
Seems that by now, every one in the industry realizes that multi-language verification environments are not a faraway vision, something only for eccentric verification experts. Multi-language is here,...
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Multi-Language Verification Environment (#2) – Passing Items on TLM Ports,...
In the previous blog post, we created a simple multi-language verification environment, running UVCs implemented in SystemVerilog and in e.The architecture of the environment is as pictured here: We...
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It’s Time to Modernize Debug Data and It’s Happening at DAC
“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog 1364-1995 and the open VCD syntax standard for debug data interoperability. Now the leading edge is over 1 billion...
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Multi-Language Verification Environment (#3) – Connecting UVM Scoreboard to a...
In the previous blog post, we demonstrated connecting a checker implemented in SystemVerilog to a monitor implemented in e.In this post, we will show a fast way for adding a system-level data checker –...
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Multi-Language Verification Environment (#4)—Multi-Language Hierarchy
In the previous posts in this series on Multi-Language Verification Environment, we created a multi-language environment containing UVCs implemented in e and SystemVerilog. This environment is...
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Aargh!!! How Can I Read Arguments from the Command Line Without argv?
Many times a user would like to be able to modify the behavior of a program based on arguments on the command line. Let’s take as an example a user who would like to pass the name of a file which...
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Debugging Multi-Language Verification Environments
As shown in previous blog posts in the Multi-Language Verification Environment series, creating multi-language verification environments is not difficult. Using UVM-ML, we can pass data between...
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The Dark Side of Constraints on 'do-not-generate' Fields
The art of expressing hardware functionality through constraint language is often one of the trickiest parts of functional verification. Unlike procedural actions that are executed locally one by one,...
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Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)
When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But sometimes there is a need to know the exact multi-value logic, or to write an mvl value (e.g., init the signal to...
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Extending the e Language with Anonymous Methods
We're happy to have guest blogger Thorsten Dworzak describe how he added anonymous methods to the vlab_util package from Verilab. So here it goes:Many programming languages like Python, Perl, and Ruby...
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Make Your Debugging Faster by Recording Your Simulator
One of the famous quotes of Brian Kernighan is: "Debugging is twice as hard as writing the code in the first place. Therefore, if you write the code as cleverly as possible, you are, by definition, not...
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Modelling a Value Holder Template with the Value “new-ed” by Default
In many companies, there is a well-defined flow for handling monitored data items: match the input data to output data (or, match a response to a request), update data, for example latency or the time...
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RTL Signoff vs. Functional Signoff
The notion of signoff has many layers to it, both in terms of complexity but also in terms of meaning. In my last blog post, I talked about some of the imprecise attributes of functional verification,...
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Building Efficient Scoreboards
A “scoreboard” is a verification component that checks the data sent to the DUT against the data received from the DUT. The fundamental flow of the scoreboard is simple:Items sent to the DUT are added...
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Simulation Acceleration—Maximizing Simulator Performance
"Simulation Acceleration” or “Accelerated Verification” are terms commonly used to describe a verification environment in which the Device Under Test is synthesized and runs on the emulator, while...
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How to Find Where Declared e Entities Are Used
The e Reflection API allows you to perform various queries on entities in your own code, and to figure out which types, fields, methods, and so on have been declared in the code, the relations between...
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Why Do We Need a Verification Language?
This month, we celebrate the 20th anniversary of Specman’s introduction to the public—at DAC 1996 in Las Vegas. This introduction was not simply of a new tool—it was the introduction of a new concept....
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Fine Tuning of Coverage Model Definition
Functional Coverage is one of the main means to measure the quality and progress of the verification project. We define coverage models, run semi-random tests, and every once in a while analyze the...
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Coverage Maximization
Searching for “automatic coverage maximization” results with ~16 million hits. Alas, this does not reflect 16 million solutions, rather it is an indication of the big interest in this topic, and the...
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What is ISO 26262 and Why Should I Care?
ISO 26262 is a functional safety standard applied to the development of electrical and/or electronic (E/E) systems in automobiles. It is aimed at reducing risks of physical injury or of damage to the...
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