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Mode Support for SimVision “Stop Simulation” Button
Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation" button would stop the simulation both in an HDL context and in a Specman context if Specman was present in...
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New Specman Coverage Engine - Extensions Under Subtypes
This is first in a series of three blog posts that are going to present some powerful enhancements that were added to Specman 12.2 in order to ease the modeling of a multi-instance coverage...
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Introducing UVM Multi-Language Open Architecture
The new UVM Multi-Language (ML) Open Architecture (OA) posted to the new UVMWorld is the result of a collaboration between Cadence and AMD. It uniquely integrates e, SystemVerilog, SystemC, C/C+, and...
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How Can You Continue Learning About Advanced Verification at Your Desk?
How much time do you spend "playing" and "learning" before you try a new EDA tool, feature, or flow?Do you really take a training class and sift through the documentation or books about the subject...
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The Art of Modeling in e
Verification is the art of modeling complex relationships and behaviors. Effective model creation requires that the verification engineer be driven by a curiosity to explore a design's functionality,...
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Fujitsu Gets 3x Faster Regression with Incisive Simulator and Enterprise...
Verification regression consumes expensive compute resources and precious project time, so any speed-up has both a technical and business impact. As announced July 17, Fujitsu was able to improve both...
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New Specman Coverage Engine (Part II) - Using Instance-based Coverage Options...
In the last coverage blog, we showed how the extensions of covergroups under when subtypes can help us write a reusable per-instance coverage.We described a test case where a packet generator unit can...
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That Cowbell Must be Registered – Introducing the UVM SystemVerilog Register...
In May of 2012 we launched the initial cowbell YouTube video series on the basics of UVM for SystemVerilog IEEE 1800 and e IEEE 1647.This was followed by a video series on debugging with...
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New Specman Coverage Engine (Part III)—Use of Extension Under "when" vs....
In both previous coverage blog posts (Part I and the Part II), we showed two solutions for refining instance-based coverage in a reusable way. And in doing so, we demonstrated a case where using the...
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Configurable Specman Messaging Webinar Archive Available Now
Configurable Specman Messaging for Improved ProductivityWebinar Archive Available Now!Hello Specmaniacs:Ever wondered how to switch on all messages, or how to switch all of them off? Or get confused by...
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e Macro Debugging
When creating a testbench using the MDV methodology, you want to write intelligent code whose behavior can be easily modified.Using e macros can greatly improve your productivity by raising the level...
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Generic Dynamic Run-Time Operations with e Reflection, Part 1
Untyped Values and Value HoldersThe reflection API in e not only allows you to perform static queries about your code, but it also allows you to perform dynamic operations on your environment at run...
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Coverage Unreachability UNR App - Rapid Adoption Kit
The Cadence Incisive Enterprise Verifier (IEV) team recently developed a self-help training kit - a Rapid Adoption Kit - to help users gain practical experience applying IEV's Coverage Unreachability...
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Covering Edges (Part I) – Cool Automation
With random generation, most of the fields are due to be quite well covered. If the field is of a type with a wide space, e.g. address is of 32 bits, then most likely not each and every of the...
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Test Your Units Before Your Units Test You — Testing Your Testbench
Bugs are a part of life in any complex software development project. This is no different in the testbench development world. Most bugs get discovered eventually. The question is: At which stage of the...
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Practical Guide to the UVM for $15 - Virginia, There is a Santa!
Wondering what to get the verification engineer on your list? You know, the one with the zealous love of SystemVerilog and UVM? It's the Practical Guide to Adopting the UVM, Second Edition for only...
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Generic dynamic run-time operations with e reflection Part II
Field access and method invocationsIn the previous blog, we explained what are untyped variables and value holders in e, and how to assign and retrieve values to/from them. In this and the next blogs,...
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ADI Success Verifying SoC Reset Using X-Propagation Technology - Video
Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity for verifying SoC reset. In November 2013 at CDNLive India they presented a paper detailnig the new technology...
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Covering Edges (part II)—“Inverse Normal” Distribution
In the previous example, we used the "select edge" to generate edge values for fields. But in many cases, what you really want to generate is not the exact edge, but "near the edges". For example, for...
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Cadence and AMD Add New UVM Multi-Language Features
0 0 1 454 2594 Cadence Design Systems 21 6 3042 14.0 Normal 0 false false false EN-US JA HE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0;...
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