Clik here to view.
Advancing Digital Verification with Dynamic Duo III's Accelerated Computing
In an era where the complexity of chip design is accelerating at an unprecedented rate, Cadence's latest innovation, the Dynamic Duo III, emerges as a beacon of advancement for chip design teams...
View ArticleClik here to view.
USB4 Version 2.0 – Gen4 Link Recovery
USB4 Version 2.0 specification was released by the USB Promoter Group two years back. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in...
View ArticleClik here to view.
Unraveling the Newly Introduced Segmentation in PCIe 6.0
Overview The PCIe protocol evolved to its sixth generation in 2021, doubling its transfer rate to 64 GT/s compared to the previous generation and bringing new features and optimizations to move...
View ArticleClik here to view.
Navigating the Future of EDA: The Transformative Impact of AI and ML
The landscape of electronic design automation (EDA) is undergoing a monumental transformation. The catalysts? Artificial Intelligence (AI) and Machine Learning (ML). These technological marvels are not...
View ArticleClik here to view.
Tools of the Future: How Cadence Is Using AI to Change Verification
Generative AI is sweeping through every industry, re-writing the way things are done across the world. Tasks that previously required manual repetitions can now be freely automated, letting companies...
View ArticleClik here to view.
Unveiling NOP Insertion Hint: A Performance Optimizer in CXL 3.0
Compute Express Link (CXL) is a high-speed interconnect standard that facilitates efficient, low-latency communication between processors, memories and accelerator devices such as GPUs. CXL surpasses...
View ArticleClik here to view.
Unraveling the PCIe ECN Unordered IO (UIO) Feature
IntroductionUnordered IO (UIO) ECN is included in the PCIe 6.1 specification and defines a new wire semantic and related capabilities for addressing the limitations of the PCI/PCIe fabric-enforced...
View ArticleClik here to view.
Industry's First Adopted VIP for PCIe 7.0
Overview of PCIe 7.0 TechnologyPCIe technology has evolved over three decades, marking its 30th anniversary with the unveiling of PCIe 7.0. This latest standard doubles IO bandwidth to 128GT/s,...
View ArticleClik here to view.
PCIe 6.0 Address Translation Services: Verification Challenges and Strategies
Address Translation Services (ATS) is a mechanism in PCIe that allows devices to request address translations from the Input/Output Memory Management Unit (IOMMU). This is particularly important where...
View ArticleClik here to view.
Debugging SystemVerilog Constraint Randomization: A Comprehensive Guide
IntroductionSystemVerilog constraint randomization is a powerful methodology for generating realistic and diverse test scenarios in the realm of hardware design verification. However, like any complex...
View ArticleClik here to view.
Enhancing Verification Processes with Session Composer: A Path Toward Efficiency
The complexity and volume of regression tests can be overwhelming in the domain of software and hardware verification. As systems grow more intricate, ensuring their reliability requires more...
View ArticleClik here to view.
Verification Using Near End Loopback
Near End Loopback (NELB) is a feature introduced by Intel's PHY Interface spec revision 6.1, and its general idea is to facilitate testing the PHY device for high-volume manufacturing. The loopback...
View ArticleClik here to view.
Demystifying Verification of PCIe 6.0 Equalization
The PCI-SIG Developers Conference 2024 is poised to be the premier event for professionals in the computing and technology sectors. Designed to unite experts and innovators worldwide, the conference...
View ArticleClik here to view.
Unravelling L0p Updates on the PIPE Interface
Power saving is an important aspect in PCIe devices and to leverage this, PCIe6.0 has introduced the L0p feature, which is a substate of the L0 LTSSM state intended to save power by disabling lanes....
View ArticleClik here to view.
Mastering Triage in Verisium Manager: A Complete Guide
In today's complex verification environments, managing debug tasks efficiently is crucial for project success. Verisium Manager, a powerful verification management tool, offers features to streamline...
View ArticleClik here to view.
Evolution of AMBA CHI Protocol: Introducing Issue G Update
After the significant CHI Issue F update that introduced a number of important new features, Arm pushed forward with yet another significant update. The two salient features – Memory Encryption...
View ArticleClik here to view.
Root Cause Your Regression Failures Faster with Verisium PinDown
Use Verisium Pindown to identify the specific code commits that caused your regression failures using its AI enabled bug prediction capabilities, and fix them automatically.(read more)
View ArticleClik here to view.
Replay Attack Over IP Networks and its Protection Mechanism
In today's interconnected world, ensuring the security of data transmitted over networks is paramount. Internet Protocol Security (IPsec) protocol plays a crucial role in achieving these objectives by...
View ArticleClik here to view.
Verisium SimAI: Maximizing Coverage, Minimizing Bugs, Unlocking Peak Throughput
Navigating the complexities of maximizing efficiency in random testing for designs with multiple operational modes is a formidable challenge. Achieving comprehensive coverage across such varied designs...
View ArticleClik here to view.
Unlocking the Secrets of Next-Gen Verification
In the world of electronic design automation (EDA), verification is the glue that holds everything together. It's the crucial step that ensures designs function flawlessly before hitting production,...
View Article