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CXL Enumeration: How Are Devices Discovered in System Fabric?
PCIe designed system fabrics rely on software enumeration by Operating System (OS) for device discovery. CXL 2.0 device is exposed as PCIe native endpoint and CXL 1.1 is exposed as root complex...
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PCIe Lane Margining - What changed from Gen4 to Gen6?
With new PCIe 6.0 Base specifications rolled out, the move from NRZ (non-return-to-zero) to PAM4 (4-Level Pulse Amplitude Modulation) is no surprise. To address the Nyquist frequency issues at 64GT/s,...
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How Renesas Reduced Automotive SoC Verification Time
The automotive world is conquering new technological heights, piggybacking on advanced semiconductor components. A typical vehicle has around 1,400 semiconductor components, and the numbers are...
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How to Verify Complex PIPE Interface Based PHY Designs?
High-end SOC architectures today requiring more area and higher speed to transfer and process data. To fulfill this requirement, protocol such as PCIe, USB, DP, SATA and USB4 are regularly being...
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Training Insights – Webinar – Automating Bug Tracking with Verisium Debug and...
Join Cadence Training and Principal Application Engineer Daniel Bayerfor this free technical training webinar.The Verisium Debug Platform is optimized for scalability, supporting debugging of...
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Understanding Latency versus Throughput
One of the effects of adopting a High Level Synthesis design methodology is that the barrier between "Systems designers" and "Hardware designers" is substantially reduced if not totally eliminated....
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Training Insights - Brand New Free Online Course on Perspec System Verifier...
Cadence® Perspec System Verifier is a portable stimulus, system-on-chip (SoC) verification solution. The Perspec System Verifier improves SoC quality and saves time by reducing development effort for...
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Be Optimistic About Xcelium's New X-Pessimism App!
In simulation, X-Propagation has been used to track how unknown states or signals move through a design at RTL. These “Xs” can cause areas of a design to malfunction once the design has been...
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Accelerate Your Debug with Verisium - Cadence's Next-Generation Debug Solution
Debugging low-power designs is its own unique challenge in the verification field. Between confirming varying requirements across different power domains and the challenges associated with assuring...
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USB4 Version 2.0 – Link Configurations
USB4 Version 2.0 specification was released by the USB Promoter Group earlier this year. This specification enables up to 80Gbps link speed per direction in symmetric mode and 120Gbps link speed in...
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Maximise Verification Reuse with Cadence Perspec System Verifier
Are You Tired of Countless Hours Manually Creating Complex System-Level Coverage-Driven Tests to Verify Your SoC? During the verification process, teams often work independently, creating test suits...
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Insights Into the Evolutions and Optimizations of PCIe 6.0
The PCIe protocol (Peripheral Component Interconnect Express) had its first generation in 2003, being a huge breakthrough in the industry by allowing up to 2.5 GT/s per lane in a serial computer...
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Leveraging AI to Optimize the Debug Productivity and Verification Throughput
The impact of semiconductors on various sectors cannot be overstated. Semiconductors have revolutionized our operations from the automotive industry to IoT, communication, and HPC. However, as demand...
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Ethernet Encryption: Harnessing the Power of IPSec Shields
In the ever-expanding domain of interconnected devices and digital communication, ensuring the security of data transmission has become paramount. One robust solution that stands at the forefront is...
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Revolutionize System Verification Flow with a Holistic Approach
The increasing functionality of designs is leading to a noticeable rise in the complexity and efforts needed for their verification. The surge in verification efforts is not confined to hardware...
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Automate Regression Failure Triage with the Cadence Verisium
Have you ever experienced the frustration of fixing a bug during the design stage only to discover additional bugs while trying to fix the existing one? As a verification engineer, this can be a common...
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Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0
In the rapidly evolving landscape of data centers, ensuring cache coherence in multi-host environments is imperative. The Compute Express Link (CXL) 3.0 specification introduces a robust mechanism...
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Building Verification Infrastructure for Complex PCIe Verification
IntroductionPCIe (Peripheral Component Interconnect Express) is a high-speed serial interconnect that is widely used in consumer and server applications. Over generations, PCIe has undergone...
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DisplayPort 2.1 vs DisplayPort 1.4: A Detailed Comparison of Key Features
DisplayPort is a digital display interface developed by the Video Electronics Standards Association (VESA) for connecting a video source to a display device. It is known for its high bandwidth and...
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Unraveling PCIe 6.0 Loopback and Digital Near-End Loopback Feature
PCIe spec has given a specific LTSSM state named Loopback, which is intended for test and fault isolation use.Basically, it gives a mechanism that involves looping back the data that was received in...
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