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The Best Way to Learn SystemVerilog Accelerated Verification with UVM –...
UVM is a heavily used, standard, proven, easy-to-use, automated verification methodology in our current industry. With the growing use of UVM methodology, engineers need to have an in-depth knowledge....
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Xcelium ML: The Next Big Thing in Regression
Looking for that extra kick in your regression performance? Cadence’s Xcelium Logic Simulator has a new feature just for you. Harnessing the power of machine learning, which is one of the areas of...
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Mellanox's Tips and Tricks for Maximizing Your Palladium Unit
Looking to learn more about the best practices for emulating today’s billion-gate-plus designs? Rest assured—we’ve got you covered. Cadence has been partnered with Nvidia Mellanox for years, helping...
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Cadence Is Arm-and-Arm with Arm: Fast Models for Fast Prototyping
If you’re not familiar with the Arm/Cadence collaboration, you’ve been missing out. Arm has been using Cadence’s virtual system platform—Palladium® Z1 for emulation and Protium S1 for prototyping—for...
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JasperGold FPV: Asynchronous Designs? No Problem!
Asynchronous designs happen. They’re not particularly easy to verify, but sometimes they’re necessary. If you don’t have a system clock, or if you have controllers that operate at a high speed with low...
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Renesas Sees Success With the Full System Solution
If you’re looking for an example of how well the Cadence flow fits together, look no further than Renesas and their experience using the Cadence System Testbench Generator and System Performance...
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Ouch that’s Hot! Register Access Heatmap
We’re proud to see that many expert verification teams exploit the powers of UVM vr_ad, in implementing intricate verification environments in e. The vr_ad is an open source package, part of UVM-e. It...
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Have You Ever Wanted to Learn Specman/e and Did Not Know How?
As a verification engineer, you want your toolbox to be varied and rich. It looks trivial, but if we really ask ourselves why, there are several reasons. First, when you look for your next exciting...
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Training Insights - Still Relying on Static-Only CDC Signoff? Introducing the...
RTL designers are creating increasingly complex designs, and are under relentless pressure to provide assurance that the designs are complete and correct, before handing off the designs for RTL...
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Xcelium Provides 3X Performance Increase for StreamDSP's FPGA-Based Defense IP
The FPGA market is rapidly growing in the traditional Aero-Defense sector as well as in the emerging sectors like Automotive and IoT. FPGA design is considered relatively simple compared to the...
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Higher FLASH Throughput for Your Next SoC Design
Memory is an important part of every electronic system, still it is increasingly becoming a performance bottleneck. While NAND flash is primarily important in consumer and computing applications, there...
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Training Insights - Clean RTL Faster Without Simulation! Here’s How.
RTL designers are challenged by increasingly complex designs. They’re also expected to deliver higher quality RTL to verification teams under tight schedules. And teams want to expose bugs as soon as...
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HyperRam as DRAM for Some Applications!!!
Applications like Automotive, Industrial control panels, Smart Home, Smart watches, smart speakers and bends require Low cost, Low power consumption, High computing efficiency, Easy to control and Low...
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DisplayPort 128b/132b Concurrent LTTPR Link Training
Before a video frame can be sent, the Source (DP-TX) must complete link training (LT) with the downstream devices. DisplayPort (DP) version 2.0 specification mandates support for a 128b/132b link layer...
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Taking LPDDR5 to the Next Level
To cater to ever-increasing bandwidth demands from low-power DRAMs especially for devices like cell phones, tablets and others with limited power budgets, JEDEC has extended the clock frequencies...
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Webinar: Extend the Language Using Specman e Macros!
Using Cadence® Specman® Elite macros lets you extend the e language ─ i.e. invent your own syntax.Today, every verification environment contains multiple macros. Some are simple “syntax sugaring” and...
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Transport Layer – The Backbone of a USB4 Router
It won’t be incorrect to say that the transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services...
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Verifying Protocol Tunneling with Cadence USB4 VIP — The Multiprotocol Advantage
All the workings of USB4 protocol are primarily about how to transfer the native protocol data through tunneling from their originating points to respective destinations. One may verify thoroughly the...
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TileLink: Chip-Scale Cache-Coherent Interconnect Protocol
RISC-V, an open specification of an Instruction Set Architecture (ISA), which was designed to be scalable for a wide variety of applications has been enjoying wide-spread adoption in the...
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CCIX Coherency: Verification Challenges and Approaches
Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the...
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